BY Sanjib Acharya Engg. Technical Leader, GE Intelligent Platforms.
One of the Electromagnetic Compatibility (EMC) tests performed to test the immunity of electrical and electronic products or systems against Electrostatic Discharge (ESD). The ESD test procedure described in standard such as IEC 61000-4-2 aims to create a method of applying ESD which would closely simulate the actual ESD occurring from human body (operator) to the equipment directly, through a metal body of a tool (e.g. screw driver) or indirectly through an adjacent object. Preventing the paths for unintended discharge through air, proper shielding of unavoidable open traces close to the PCB edges (e.g. LED pads), providing chassis ground path for the exposed metal bodies are some of the common practices followed to make the electrical and electronic equipment immune against ESD test voltage levels.
One important aspect which is often missed out is the possibility of radiated fields generated from the ESD current disturbing the functionality of the equipment. The standard IEC61000-4-2 provides information about the radiated fields from human-metal discharge and from ESD generators but this gets un noticed sometimes till such a scenario is experienced. In this paper, two case studies are presented to explain both of these types of failures.
Keywords—EMC; Electrostatic Discharge (ESD); Eqipment Under Test (EUT); Conducted; Radiated;
Electrostatic Discharge (ESD) is one of the electro-magnetic disturbances, which might cause damages to the components in an electronic circuit or might upset the functionality of an electronic circuit board. The standards such as IEC61000-4-2 describe the procedures for testing electrical/electronic equipment. The test procedures include subjecting the EUT to ESD generated by an ESD simulator or more commonly known as ESD gun in three modes: air discharge, direct discharge and indirect discharge. It is relatively easier to anticipate and to prevent potential failures due to ESD current finding low impedance path through sensitive circuitry by direct conduction. On the other hand it is always challenging to imagine the probable mechanisms of failure of an electronic circuit due to the secondary effects of an ESD event: secondary discharge caused by the primary discharge or the radiated Electric-field or Magnetic-field coupled to the electronics under test.
In the following sections of this article, the primary and secondary effects of ESD are illustrated with the help of real-life case studies of product failures due to ESD.
II.FAILURE MODES DUE TO ESD
A. Failures due to primary effect of ESD event
The primary effect associated with an ESD event is the intense electrostatic field created by the charge separation prior to the ESD arc, followed by the intense arc discharge current flowing though the affected circuit, causing functional failure and most of the time causing irreversible damage to the components if not protected, causing damage to the traces on the Printed Circuit Board (PCB), insulation etc.
It is possible to identify the weak areas in the design, which could get affected by the primary effects of the ESD. Any unguarded traces, connector pins, component pads (e.g. LED pads) near to the board edge and closer to the vents on the enclosure, the metallic parts such as the connector shells not grounded properly, the unprotected connector (user accessible port) pins are such candidates for which care must be taken to prevent failures due to direct arcing.
B. Failure due to secondary effects of ESD event
The following secondary effects can be caused by the arc discharge current caused by an ESD event:
- Secondary arc or discharges (generally due to any ungrounded metallic part to the circuitry close by).
- Capacitive coupling or the electric field coupling to the product’s electronic circuits (predominantly high-impedance circuits).
- Inductive coupling or the magnetic field coupling to the product’s electronic circuits (predominantly low-impedance circuits).
Direct discharge or discharging through air on any exposed metallic part on the product could cause formation of secondary discharges to the electronic circuits adjacent to the affected metallic connections, which could upset the functionality or even could cause damages to the product. This could happen if proper clearances are not maintained for the affected circuits from the exposed metallic parts such as shield or chassis ground connections.
The arc current also creates electric and magnetic fields (predominantly near-field) that could couple to circuits and induce unintended voltages and currents in the affected circuits. The coupling could also happen through the cables attached to the product and then the induced current could conduct into its circuitry. The placement and geometry of ground traces, ground circuit connections, board location, and orientation within the chassis are all critical in minimizing inductive pickup from the radiated magnetic fields . It indeed is a challenging task to anticipate the failure mechanisms due to the radiated field caused by the ESD current getting coupled capacitively or inductively to the electronic circuits.
III. CASE STUDY: PRIMARY EFFECT OF ESD
Usually the electronics circuit could be protected against the primary effect of ESD if proper attention is given during design. The basic idea is either to prevent a discharge happening on sensitive circuits by providing insulated barrier, cover or cap etc. or to divert the discharge current by providing a guard trace to the ground.
The electronics design involved in the first case study is a multi-channel Discrete Input card for industrial automation equipment. The design included a 2-layer PCB that was enclosed in a plastic casing, which had vents on the top and bottom for thermal convection cooling of the electronics circuit. There were LED arrays towards the top, front corner of the PCB for indicating the channel status when the board is operational in the field.
A. Description of the failure mode
While performing the air discharge, it was observed that, discharge occurred through the plastic cover vents on to the pads of the LEDs which were much closed to the top edge of the PCB and since these LEDs were controlled by the IO port pins of a microcontroller. Due to the same, the microcontroller stopped working. The microcontroller did not recover unless it was power cycled. After the ESD was repeated several times during the experiment, eventually there was a permanent failure and the board did not recover after it was power-cycled.
Figure 1: Location of the failure due to ESD
B. Solution to the problem
It was obvious that the discharge occurred because the LED pads were very close to the edge of the PCB and when the ESD gun was brought near to that place, the air-gap was ionized due to the electrostatic field and eventually the arc broke through the air-gap. Since the LED array could not have been moved away from that location of the PCB or shape of the PCB or plastic covers could not have been altered due to mechanical constraints, a masked trace was routed near the top edge of the PCB, which was connected to chassis ground connection as shown in Figure 2. This bare trace acted like a “guard trace” and diverted the ESD directly to the chassis ground before it could reach the LED pads.
Figure 2: Guard trace prevented the failure
There could have been several solutions to fix this issue including designing an insulating cap covering the LED array pads concealing any air gaps in order to prevent ESD occurring through air. It would depend on the convenience of implementing a solution best on the time & resources needed and cost of implementation involved.
IV. CASE STUDY: SECONDARY EFFECTS OF ESD
The electronics design presented in this case study is a processor board. The electronic assembly had three PCBs in it: main board PCB A and two daughter boards PCB B and PCB C. The PCB A and PCB B constituted microprocessor based digital circuits and the PCB C constituted switched mode power supply (SMPS) circuitry which derived required voltage & power for the PCB A and PCB B from an external AC/DC source. The PCBs A, B and C were stacked together using board-to-board connectors as shown in Figure 1 below. The PCB A and PCB B were enclosed in one plastic enclosure and the power supply PCB# C was enclosed in a separate plastic enclosure, which had cooling vents on all four sides.
Figure 3: PCB Stacking and Board-to-Board Connectors
In Figure 3, the Board-to-Board connectors only are shown. The picture on the top in Figure 3 showed how the three PCBs are stacked together when seen from the bottom side. The picture on the bottom showed the relative locations of the Board-to-Board connectors and the PCBs when seen from the front side of the EUT when mounted on the DIN rail. The plastic enclosures are omitted from the Figure 3.
There were two shielded communication ports on PCB A as shown in Figure 4. The port 1 was a shielded RS485 port (15-pin D sub connector) and the port 2 was a shielded Ethernet port (RJ45 connector). The port 1 was controlled by the microprocessor on the main PCB A and the port 2 was controlled by other microprocessor on the daughter PCB B. Once the EUT was mounted on the DIN rail, the shield connections of port 1 & 3 got electrically connected to the DIN rail. The DIN rail was mounted to a panel, which was connected to the ground reference plane (GRP) by a braided copper cable (>1 meter).
Figure 4: Position on Port 1 & 2 on PCB A
A. Description of failure mode (due to ESD)
While performing ESD testing on Port 1 (RS485), failure of Port 2 (Ethernet) functionality was observed for contact discharge of 4.0KV. It was noted that Port 1 functionality was not disturbed. As mentioned earlier, the Port 1 functionality was controlled by a microprocessor on the main PCB A whereas the Port 2 functionality was controlled by another microprocessor on PCB B. Interestingly no failure was observed on Port 2 while doing the contact discharge of 4.0KV. It was double checked that shield connections of both Port 1 & Port 2 were electrically connected to chassis ground (through the DIN rail). It was further observed that even if the discharge was made on the DIN rail (connected to GRP) near to Port 1, Port 2 functionality stopped. The port 2 functionality did not recover until the module was power cycled. Further investigation revealed that the microprocessor on the daughter PCB B was getting stuck to an unknown state during the ESD event and needed a reset signal (or power cycle) to resume its functionality (to resume Port 2 functionality).
B. Experiments conducted to debug the issue
In order to debug this issue and to understand the nature of the failure further, the following experiments were carried out.
a) First it was checked if the failure occured due to the disturbance caused by the ESD voltage on the chassis ground connections on the PCB A. In real world the braided copper cable which connected the EUT ground to GRP, had certain inductance. So, it was likely that the ground voltage of the EUT was elivated momentarily a high voltage at the time of ESD strike. But the failure was unlikely due to this as the voltage of the entire circuit also would rise accordingly. To examine further, the EUT was kept on the GRP with an insulation in between the GRP and the EUT as shown in Figure 5. Then the discharge was made on the GRP around the EUT. It was observed that failure still occurred when the discharge was made on the GRP closer to left-side of the EUT (where the Port 1 was located). The discharge points on the GRP where the failure of Port 2 functionality was observed is marked with red crosses in Figure 5 below.
Figure 5: Failure occurs even with ESD on GRP
Doing this experiment, it was learnt that the Port 2 functionality failed even though the ESD voltage did not get applied direct to any electrical connections on the EUT as the EUT was insulated from GRP. Note that the power supply card (PCB C) also was getting power from an isolated source. The only possibility that was prominent was the ESD voltage or current resulting in E or H field, that was probably getting capacitively or inductively coupled with some circuitry in the EUT causing the failure. Another possibility was – it could been due to the RF noise from the gun getting coupled with the EUT (near field) and was causing the upset.
b) Some more experiments were conducted to identify which circuitry was getting affected. Since the Port 2 functionality was getting interrupted, which was controlled solely by the microprocessor and the circuitry on the PCB B. The PCB B was getting power from PCB C (power supply) and the traces were passing through PCB A, but as the functionalities on PCB A did not get affected by the field generated by the ESD, PCB A was not looked into for further investigation to start with.
From the previous experiment, it was learnt that the ESD generated E/H field getting coupled to EUT circuit and caused failure of PCB B functionalities. Hence PCB B was wrapped around with a copper tape with a layer of mylar sheet as the insulating material in between. The copper envelop was cut near the board-to-board connector pair to allow connection between PCB A and PCB B ensuring minimum openning. The copper envelop acted like a shield when it was connected to the ground plane on the EUT. The modified EUT was installed on the DIN rail and the contact mode ESD test was carried out at 4.0KV. Unfortunately shielding of PCB B did not help and the the failure of Port# 2 was still observed.
c) Since shielding PCB B alone did not help, it was decided to isolate PCB C (power supply) by keeping it physically away from the EUT by using a short flexible cable connecting PCB# C to PCB# A as shown in Figure 6.
Figure 6: PCB# C was physically separated from EUT
The EUT was installed on the DIN rail and the contact mode ESD test was carried out at 4.0KV. Interestingly EUT passed the ESD test this time when contact discharge was made on Port 1 and Port 2 with out any functional interruption.
C. Inferred causes of the failure
From the three experiments described in the previous section, the following causes of the failures were inferred:
- The failure of Port 2 functionality observed while performing ESD testing was due to the ESD generated E or H field getting capacitively or inductively coupled to EUT.
- It is observed that moving the power supply module (PCB C) a little away from the EUT made a big difference as the same failure did not occur. Hence it was most likely the power supply which was getting affected due to the ESD generated field.
- Since it was the power supply circuit (low impedance) which was affected, it was probably due to H-field (inductive coupling) or the radiated noise from the ESD gun which caused failure
- The disturbance generated in the power supply card gets propagated to the PCB A and PCB B, mostly conductively. The functionality of PCB B got affected while the functionality of PCB A was unaffected. This could be mostly due to the fact that the frequency of operation of the of the processor on the PCB B was much higher (>100MHz) as compared to the other processor on the PCB A. The frequency of the noise generated by the ESD pulse usually contains frequency components as high as 300MHz – 2GHz. Another possibility could be that the processor circuitry on PCB B was more sensitive to noise due to lesser noise margin.
- As there was a strong change with keeping the power supply PCB C a little away, it was mostly the inductive coupling which caused failure rather than the radiated noise from the gun, as there is a weak change with distance(1/r) for the radiated noise as compared to a strong change in distance (1/r2 or 1/r3) for the capacitive of inductive coupling .
D. Solution to the problem
First, the thought that occurred from the experiments conducted was that the nature of the noise generated by the magnetic field during ESD event, which upset the functionality of the processor circuitry on the PCB B was probably common-mode in nature. Hence the first thing that was tried was to install a common mode filter (with ferrite core) at the power inlet of the PCB A. The common mode filter had impedance greater than 500ohm @ 100MHz, which was pretty decent for blocking common mode high frequencies. The characteristics of the common mode filter have a broad band width as shown in the picture below:
Figure 7: Impedance vs Frequency Plot for the CM filter 
After the common mode filter (CM filter) was installed at the power entry on the PCB A, the filtered supply (as indicated as V_FLT in Figure 8) was supplied to circuitry on the PCB A and PCB B.
Figure 8: EUT with the CM filter
The EUT with the CM filter was taken through the ESD test, which could finally pass contact discharge upto 4.4KV and air discharge upto 8.8KV without any interruption of functionalities.
E. Conclusions drawn
Since the failure was avoided by implementing the CM filter, the following conclusions were drawn about the cause of the failure:
1) The noise on the power rail caused by ESD pulse was indeed “conducted” from the power supply (PCB C) and it was common mode in nature.
2) The power supply (PCB C) was getting affected due to the E-field or the H-field generated by the ESD pulse. Most likely it was due to inductive coupling with the power supply components or PCB, as the power supply is a “low impedance” circuit which is mostly affected due to inductive coupling with the magnetic field .
V. KEY TAKEAWAYS
From the above case study, the following key takeaways are summarized below:
1) ESD not only causes the energy to flow through the path of the discharge due to the injected ESD current, the also generates strong electro-magnetic field, which has the potential to upset functionality of electronic circuits. Electronics circuits would need protection against both of types of failures.
2) It is relatively easier to visualize & prevent the probable faulire due to the primary effects of ESD as compared to the failures due to the secondary effects of ESD.
3) It is very important to keep the impedance of the ground return (or chassis ground) connection as minimum as possible as in reality the ground wire connections has a substantial amount of inductance if it is lengthy.
4) The large instanteneous current due to the ESD can induce large magnetic fields on the application printed circuit board (PCB) and chassis. The placement and geometry of ground traces, ground circuit connections, board location, and orientation within the chassis are critical in minimizing inductive pickup from the magnetic fields caused by the ESD current.
5) Plastic cases are bad as compared to the metal cases while protecting the electronics inside against the magnetic field coupling. The metal cases would be better as the same will shield the electroning from magnetic field. But the metal casing also could be equally error prone due to openings, vents, improper grounding, improper cable shielding.
6) For low impedance input circuitry the technique of blocking high frequency noise by placing impedance in series (such as using Common Mode choke, ferrite beads) is more effective as compared to using capacitors as filter. On the other hand for high impedance input circuit capacitors are more effective filters .
 Analog Devices application note AN-793: ESD/Latch-Up Considerations with iCoupler Isolation Products, by Rich Ghiorse
 Introduction to Electromagnetic Compatibility (2nd Edition): By Clayton R. Paul
 Datasheet for Common Mode Filters for power lines: ACM series from TDK
 EMC TROUBLESHOOTING TIPS, Wyatt Technical Services – EMC Consulting & Seminars, authored by Kenneth Wyatt
PROFILE OF THE AUTHOR
Sanjib Acharya, the author of this article is working as Engineering Technical Leader in GE. The author holds Bachelor of Electrical Engineering degree (1999). He has over 16 years of experience in industrial electronics design, Signal Integrity, design for EMC & compliance testing, Functional Safety (IEC 61508). The author has worked in the domains: low voltage switchgear, power supply design for telecom applications, industrial controls and process automation.